The invention relates to semiconductor power devices and more particularly to a structure and method for forming a trench gate field effect transistors (FETs) with reduced gate to drain charge (Qgd).
Power FETs are used in such applications as DC-DC converters. A key parameter in achieving a high efficiency DC-DC converter is the gate to drain charge (Qgd) of the FETs used in the converter. A known method for reducing Qgd is to use a thick bottom oxide (TBO) below the trench gate electrode. This is more clearly shown in FIG. 1A.
FIG. 1A is a simplified cross-section view of a conventional n-channel trench gate vertical MOSFET. As shown, a trench 101 extends through n-type source regions 106 and p-type well region 104, and terminates within n-type drift region 102. An n-type substrate (not shown) extends below drift region 102. Typically, source regions 106 and well region 104 are formed in an n-type epitaxial layer which would also encompass drift region 102. Such epitaxial layer would normally be formed over the substrate. Trench 101 includes a thick insulator 108 along its bottom, a gate insulator 110 along its sidewalls, a recessed gate electrode 112 (typically from polysilicon), and an insulating layer 114 atop the gate electrode 112. A source metal (not shown) contacts source regions 106 and well region 104 along the top-side, and a drain metal (not shown) contacts the substrate along the bottom surface of the structure.
While the thick bottom insulator 108 helps reduce Qgd, this parameter (Qgd) still remains a significant factor in performance of such applications as DC-DC converters. Thus, techniques for further reducing Qgd are desirable.